In electronic circuits, particularly in digital circuits, it is highly important to have a circuit which can differentiate a signal of "1" from a signal of "0" based on a reference potential. For instance, in a semiconductor memory device, a data read out from a memory cell has to be classified into either "1" or "0".
For this purpose, according to a developed method, a reference potential is given to one bit line of paired bit lines in which data are read out, and the reference potential and the readout data are compared to determine if the readout data is "1" or "0".
However, with the advancements of high density and high integration semiconductor fabrication technologies, modern semiconductor memory devices are now constituted of extremely miniaturized transistors and memory cell capacitors.
Therefore, the amount of charge storable in the memory cell capacitor is small, and the potential difference necessary to differentiate the data "1" from "0" is very small. Thus, in order to secure the reliability of data obtained from semiconductor memory devices, it is necessary to provide a highly accurate reference potential.
Moreover, since the semiconductor memory device consists mainly of dynamic random access memory (DRAM) devices wherein charge is stored in memory cell capacitors disposed therein, and data is expressed in terms of the charge in individual memory cell capacitors. Though the dielectric layer of memory cell capacitor had been made mainly of a silicon oxide layer, a semiconductor memory device using a ferroelectric layer has been developed in order to attain a nonvolatile memory device wherein the data can be memorized without extinction.
A semiconductor memory device provided with a conventional reference potential generator is now explained below.
FIG. 27 shows a circuit construction of conventional semiconductor memory device, and FIG. 28 shows an operational timing chart. FIG. 29 shows a hysteresis characteristics of ferroelectric layer which is used in a memory cell capacitor of conventional semiconductor memory device, and FIG. 30 shows a hysteresis characteristics of ferroelectric layer which is used in a reference cell capacitor of conventional semiconductor memory device.
As shown in FIG. 27, bit lines 3 and 4 are connected to sense amplifier 7, and each of the bit lines 3 and 4 is connected to memory cells 8a, 8b, 8c, 8d, and 8e and reference cells 9 and 10. Memory cell 8a is constituted of MOS transistor 11 and memory cell capacitor 13, and the gate of MOS transistor 11 is connected to word line 1. The drain thereof is connected to bit line 3, and the source thereof is connected to the first electrode of memory cell capacitor 13 while the second electrode of memory cell capacitor 13 is connected to cell plate electrode 5.
Likewise, reference cell 9 is constituted of MOS transistor 12 and reference cell capacitor 14. The gate of MOS transistor 12 is connected to reference word line 2, the drain thereof is connected to bit line 4, and the source thereof is connected to the first electrode of reference cell capacitor 14 while the second electrode of reference cell capacitor 14 is connected to reference cell plate electrode 6.
In this semiconductor memory device, reference potentials are generated by reference cells 9 and 10, and the reference potential generated by reference cell 9 is supplied to bit line 4, and the reference potential generated by reference cell 10 is supplied to bit line 3.
In this case, since the potential difference between these two reference potentials should be negligibly small, the dielectric layers of these reference cells capacitors have to be fabricated to have an extremely uniform area and thickness by applying a highly strict manufacturing process.
Then, by referring FIGS. 28 to 30, the operations of conventional semiconductor memory device are explained next. In FIGS. 29 and 30, the horizontal axes show an electric field applied to memory cell capacitor 13, and the vertical axes show charge produced by this. As shown in FIGS. 29 and 30, a residual polarization encircled by point B, point E, point K, and point H, exists even when the applied electric field is zero.
Therefore, a nonvolatile semiconductor memory device can be fabricated by utilizing this residual polarization left in the ferroelectric capacitor as a nonvolatile data. Moreover, the memory cell capacitor 13 is at a state of point B when the data in memory cell 8a is "1", and it is in a state of point E when the data in memory cell 8a is "0", providing the initial condition of reference cell capacitor 14 is at a state of point K.
Then, the data read out from memory cell 8a is explained next. As an initial condition, the bit lines 3 and 4, word line 1, reference word line 2, cell plate electrode 5, and the reference cell plate electrode 6 are set at a logical state of "L" (low level), and after this, bit lines 3 and 4 are set at a floating condition.
The word line 1, reference word line 2, cell plate electrode 5, and the reference cell plate electrode 6 are then set at a logical state of "H" (high level). Since MOS transistors 11 and 12 are set at ON at that time, an electric field is applied on the memory cell capacitor 13 and reference cell capacitor 14. Thus, when the data in memory cell 8a is "1", the state of memory cell capacitor 13 shown in FIG. 29 is shifted from point B to point D, and the charge Q1 is read out in bit line 3.
On the other hand, when the data in memory cell 8a is "0", the state of memory cell capacitor 13 is shifted from point E to point D, and the charge Q0 is read out in bit line 3. The data in memory cell 8 is read out by amplifying the potential difference between the potential of bit line 3 in which the data stored in memory cell 8a is read out and the potential of bit line 4 in which the data stored in the reference cell 9 is read out by sense amplifier 7.
Since the potentials of bit line 3 and cell plate electrode 5 are in a state of "H" after the data "1" is read out from memory cell 8a, no electric field is applied to memory cell capacitor 13, shifting the state of memory cell capacitor 13 to point E.
In order to shift the data state of memory cell capacitor 13 back to point B after this, cell plate electrode 5 is set at "L", and word line 1 is then set at "L" after state of memory cell capacitor 13 is set at a state of point A. Since no electric field is applied to memory cell capacitor 13 when word line 1 is set at "L", it is brought back to a state of point B.
Likewise, since bit line 3 is in a state of "L" and cell plate electrode 5 is in a state of "H" after the data "0" in memory cell 8a is read out, the memory cell capacitor 13 is at a state of point D. Then, after this, since the electric field applied to memory cell capacitor 13 becomes zero by setting cell plate electrode 5 at "L", memory cell capacitor 13 is set at a state of point E. Although word line 1 is set at "L" afterward, the memory cell capacitor 13 is maintained at a state of point E since it is maintained at a state of no applied electric field.
On the other hand, as for the reference cell 9, reference cell capacitor 14 is at a state of point J shown in FIG. 30 since bit line 4 is set at "L" and cell plate electrode 6 is set at "H" when the data in memory cell 8a is "1".
When reference word line 2 and reference cell plate electrode 6 are set at "L" at the same time afterward, the state of reference cell capacitor 14 is shifted back to point K since the state of reference cell capacitor 14 with no applied electric field is unchanged.
Likewise, when the data of memory cell 8a is zero, the state of reference cell capacitor 14 is situated at point K since bit line 4 and cell plate electrode 6 are in a state of "H". When reference word line 2 and reference cell plate electrode 6 are set at "L" simultaneously afterward, the state of reference cell capacitor 14 is at point K since the state of reference cell capacitor 14 with no applied electric field is unchanged.
However, in the above shown semiconductor memory device, deviations of reference potentials are often produced by the deviations of area and thickness or other factors of the ferroelectric layer since reference cell 9 provided to generate a reference potential is constituted of only one MOS transistor 12 and reference cell capacitor 14.
Moreover, right after the fabrication of reference cell capacitor, it may take any state other than that of point K. For instance, when it were at point H in its initial condition, an erratic operation in performing its very first readout operation, is possible.
Moreover, since reference word line 2 and reference cell plate electrode 6 are set at "L" simultaneously after the charge read out from bit line 3 is amplified by sense amplifier 7, the parasitic capacitance of reference word line 2 is inevitably large. Furthermore, when the fall down period of reference word line 2 is longer than the fall down period of reference cell plate electrode 6, the bit line 4 would be set at "H" and the reference cell plate electrode 6 would be set at "L" when the data in memory cell 8a is "0", and at this time, the state of reference cell capacitor 14 set at point G.
When the reference cell plate electrode 6 is set at "L" afterward, the state of reference cell capacitor 14 is set at point H shown in FIG. 30. Therefore, an erratic operation is possible at the succeeding readout operation since the state of reference cell capacitor 14 is not set at point K which represents the initial state.
Moreover, since the rises and the falls of word line 1, reference word line 2, cell plate electrode 5, and reference cell plate electrode 6 are performed simultaneously, problems of power concentration are inevitable.